Volume: 19 Issue-01 (January-June) 2024

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NOISE MARGIN AWARE POWER EFFICIENT 12T SRAM CELL WITH A HIGH READ AND WRITE ABILITY

ABSTRACT

SRAM stability is a major concern in nanometer CMOS technologies. As the most important metrics of SRAM static stability, the static characteristics of SRAM are derived by static characteristic curves (read butterfly curve, standby butterfly curve, read N curve, write N curve and WNM curve). A non-destructive column-selection-enabled 10T SRAM for aggressive power reduction is presented in this brief. It frees a half-selected behaviour by exploiting the bitline-shared data-aware write scheme. The differential-VDD (Diff-VDD) technique is adopted to improve the write ability of the design. In addition, its decoupled read bitlines are given permission to be charged and discharged depending on the stored data bits. In combination with the proposed dropped-VDD biasing, it achieves the significant power reduction. As an enhancement of this project, Reverse Bias Current eliminated, Read-separated, and Write-enhanced SRAM is proposed with 45 nm technology and 12T cells.

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